JEE Mains · Physics · STD 12 - Semicondutor electronics
- JEE Mains 2026
- Medium
- MCQ
For the given logic gate circuit, which of the following is the correct truth table?

Pick an option to check your answer.
Answer & Solution
Correct Answer
(D) n m z 0 0 1 0 1 1 1 1 0 1 0 0
Step-by-step Solution
Detailed explanation
Gate 1 : At bottom there is an OR gate with inputs n & m
out put \(=n+m\)
Gate 2 : A NAND gate, its Input are direct n & the output of OR gate ( \(n+m\) )
out put \(z =\overline{ n \cdot( n + m )}\)
since \(n .( n + m )=( n . n )+( n . m )\)
\(= n + n \cdot m = n (1+ m )= n\)
∴ output \(z =\overline{ n \cdot( n + m )}=\overline{ n }\)
out put \(=n+m\)
Gate 2 : A NAND gate, its Input are direct n & the output of OR gate ( \(n+m\) )
out put \(z =\overline{ n \cdot( n + m )}\)
since \(n .( n + m )=( n . n )+( n . m )\)
\(= n + n \cdot m = n (1+ m )= n\)
∴ output \(z =\overline{ n \cdot( n + m )}=\overline{ n }\)
| n | m | \(Z =\overline{ n }\) |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 1 | 0 |
| 1 | 0 | 0 |
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