MHT CET · Physics · Semiconductors
A combination of logic gates is as shown in figure. ' \(P\) ', ' \(Q\) ', ' \(R\) ' and ' \(\mathrm{S}\) ' are the inputs and ' \(\mathrm{X}\) ', ' \(\mathrm{Y}\) ' and ' \(\mathrm{Z}\) ' are outputs. When inputs \(\mathrm{P}\) and \(\mathrm{R}\) are 'low' and \(\mathrm{Q}\) and \(\mathrm{S}\) are 'high', the outputs \(\mathrm{X}, \mathrm{Y}\) and \(\mathrm{Z}\) are respectively

- A 0,1,0
- B 0,1,1
- C 1,0,0
- D 1,1,1
Answer & Solution
Correct Answer
(A) 0,1,0
Step-by-step Solution
Detailed explanation

\((\mathrm{x}, \mathrm{y}, \mathrm{z})=(0,1,0)\)
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